Analog-to-digital converters are well known in the art, having relatively large size and high power consumption. An analog-to-digital converter encodes an analog signal, S, as a sum of powers of 1/2: ##EQU1## where b.sub.n 's are 1 or 0, and the full scale reference is taken to be 1.0. The conventional successive approximation algorithm for determining the b.sub.n 's is to compare S with ##EQU2## for the kth bit conversion. If S exceeds R.sub.k, b.sub.k =1 and if S is less than R.sub.k, b.sub.k =0. The k+1 reference then becomes: ##EQU3## where a subtraction is involved. (b.sub.k, 0, 1 for b.sub.k =1, 0 respectively).
Stating the above nonmathematically, the signal S is progressively compared with EQU R=1/2, 1/2+1/4, 1/2+1/4+1/8, etc.
As soon as R exceeds S, the last added fraction (1/8) must be subtracted and the next in the series of (1/2.sup.n) (e.g. (1/16) added. The approximations then continue by successively adding progressively smaller members of the series (1/2.sup.n) to R until it again exceeds S, at which time the member of the series (say (1/32) which caused R to exceed S is subtracted from R and, prior to the next comparison, the next member in the series (1/64) is added to R. The process continues through a series of approximations depending in number on the desired precision of the system. Typical analog-to-digital converters, such as those formed as bipolar devices, are not easily integrated with charge coupled device hardware. Such integration may require additional hardware to act as a buffer between the charge coupled device hardware and the analog-to-digital converter. Therefore, a significant problem in the art is that integration of charge coupled devices with currently available analog-to-digital converters may require additional hardware to provide compatibility between charge coupled devices and the analog-to-digital converter.